The present invention relates to DMA (direct memory access) data transfer technology in a microcomputer system and technology effectively applied to a method for controlling queues for temporarily holding DMA transfer requests. It relates to technology effectively used for a DMA (direct memory access) controller or DMA control circuit incorporated in, e.g., a microprocessor or microcomputer.
In a system using a one chip microcomputer including a central processing unit (hereinafter referred to as CPU), and peripheral modules such as a timer circuit and a serial communication interface circuit, a DMA controller is used to enable data to be directly transferred between a memory and peripheral devices without involvement of the CPU. The DMA controller, which is sometimes configured as an LSI distinct from a microcomputer, is recently often incorporated in a microcomputer and microprocessor. Such a DMA controller may be provided with an FIFO (First In First Out) memory called a request queue in order that a next DMA transfer request can be accepted during execution of a DMA transfer.